Changeset 389

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Timestamp:
01/20/08 19:38:52 (7 months ago)
Author:
agr
Message:

CTR bug fixed in encryption in bmac

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  • nano-RK/projects/basic_adc/main.c

    r369 r389  
    8080  cnt=0; 
    8181  chan=0; 
    82   val=nrk_set_status(fd,ADC_CHAN,4); 
     82  val=nrk_set_status(fd,ADC_CHAN,5); 
    8383  if(val==NRK_ERROR) nrk_kprintf( PSTR("Failed to set ADC status\r\n" )); 
    8484  while(1) { 

  • nano-RK/projects/basic_bmac/main.c

    r380 r389  
    8181 
    8282  // init bmac on channel 25  
    83   bmac_init (25); 
     83  bmac_init (15); 
    8484 
    8585  // Enable AES 128 bit encryption 
    …… 
    128128} 
    129129 
     130uint8_t ctr_cnt[4]; 
    130131 
    131132void tx_task () 
    …… 
    148149  nrk_signal_register (tx_done_signal); 
    149150 
     151  ctr_cnt[0]=0; ctr_cnt[1]=0; ctr_cnt[2]=0; ctr_cnt[3]=0; 
    150152  cnt = 0; 
    151153  while (1) { 
    …… 
    171173    // bmac_addr_decode_disable(); 
    172174 
     175     ctr_cnt[0]=cnt;  
     176     if(ctr_cnt[0]==255) ctr_cnt[1]++;  
     177     if(ctr_cnt[1]==255) ctr_cnt[2]++;  
     178     if(ctr_cnt[2]==255) ctr_cnt[3]++;  
     179     // You need to increase the ctr on each packet to make the  
     180     // stream cipher not repeat. 
     181     bmac_encryption_set_ctr_counter(&ctr_cnt,4); 
    173182 
    174183    // For blocking transmits, use the following function call. 

  • nano-RK/projects/basic_bmac/nrk_cfg.h

    r148 r389  
    1111// NRK_HALT_ON_ERRORS will cause the kernel to freeze on errors so that 
    1212// it is easier to see debugging messages. 
    13 //#define NRK_HALT_ON_ERROR 
    14 #define NRK_HALT_AND_LOOP_ON_ERROR 
     13#define NRK_HALT_ON_ERROR 
     14//#define NRK_HALT_AND_LOOP_ON_ERROR 
    1515 
    1616// NRK_STACK_CHECK adds a little check to see if the bottom of the stack 

  • nano-RK/projects/flash_flood/client/main.c

    r386 r389  
    9090  nrk_setup_uart (UART_BAUDRATE_115K2); 
    9191 
    92   my_subnet_mac = 1; 
    93   my_mac = 5; 
     92  my_subnet_mac = 2; 
     93  my_mac = 10; 
    9494 
    9595  nrk_init (); 

  • nano-RK/projects/flash_flood/gateway/main.c

    r388 r389  
    247247    tx_buf[PKT_TYPE]=PING_PKT; 
    248248//    tx_buf[PKT_TYPE]=SENSOR_SHORT_PKT; 
    249     tx_buf[CTRL_FLAGS]=  ENCRYPT | LINK_ACK | DS_MASK  | TREE_FILTER | LED_FLOOD; 
     249    tx_buf[CTRL_FLAGS]=  ENCRYPT | LINK_ACK |  DS_MASK  |  LED_FLOOD; 
     250//    tx_buf[CTRL_FLAGS]=  ENCRYPT | LINK_ACK | DS_MASK  |  LED_FLOOD; 
    250251    tx_buf[SEQ_NUM]=cnt; 
    251252    tx_buf[PRIORITY]=0; 
    …… 
    255256    tx_buf[DS_DELAY_PER_LEVEL]=1; 
    256257    tx_buf[DS_NAV]=15; 
    257     tx_buf[DS_MAC_CHECK_RATE]=25; 
     258    tx_buf[DS_MAC_CHECK_RATE]=50; 
    258259    mac_check_rate = tx_buf[DS_MAC_CHECK_RATE]; 
    259     tx_buf[DS_RSSI_THRESHOLD]=-45; 
    260 //    tx_buf[DS_RSSI_THRESHOLD]=5; 
     260    tx_buf[DS_RSSI_THRESHOLD]=-50; 
     261    tx_buf[DS_AES_CTR_3]=0; 
     262    tx_buf[DS_AES_CTR_2]=0; 
     263    tx_buf[DS_AES_CTR_1]=0; 
     264    tx_buf[DS_AES_CTR_0]=cnt; 
     265//    tx_buf[DS_RSSI_THRESHOLD]=-30; 
    261266    tx_buf[DS_LAST_HOP_MAC]=gw_mac; 
    262267    len=DS_PAYLOAD_START; 

  • nano-RK/projects/flash_flood/include/flash_flood.h

    r388 r389  
    8282 
    8383// Common to all packets 
    84 #define PKT_TYPE               0 
    85 #define CTRL_FLAGS             1   
     84#define CTRL_FLAGS             0   
     85#define PKT_TYPE               1 
    8686#define SEQ_NUM                 2        
    8787#define PRIORITY                3        
    …… 
    100100#define DS_MAC_CHECK_RATE       12       
    101101#define DS_RSSI_THRESHOLD       13       
    102 #define DS_PAYLOAD_START        14     
     102#define DS_PAYLOAD_START        18     
    103103 
    104104// Common to upstream reply packets 
    …… 
    137137        uint8_t last_hop_mac; 
    138138        uint8_t mac_filter_num; 
     139        uint8_t aes_ctr[4]; 
    139140 
    140141// Buffer Management  

  • nano-RK/projects/flash_flood/include/pkt_packer.c

    r382 r389  
    1515      ds_pkt->ack_retry = (ds_pkt->buf[ACK_RETRY]&0xF0)>>4; 
    1616      ds_pkt->subnet_mac= ds_pkt->buf[SUBNET_MAC]; 
    17  
    1817 
    1918      ds_pkt->hop_cnt = ds_pkt->buf[DS_HOP_CNT]; 

  • nano-RK/src/net/bmac/bmac.c

    r380 r389  
    5757    // Any code here gets called the instant a packet is received from the interrupt    
    5858    return pRRI; 
     59} 
     60 
     61int8_t bmac_encryption_set_ctr_counter(uint8_t *counter, uint8_t len) 
     62{ 
     63if(len!=4 ) return NRK_ERROR; 
     64rf_security_set_ctr_counter(counter); 
     65   return NRK_OK; 
    5966} 
    6067 

  • nano-RK/src/net/bmac/bmac.h

    r381 r389  
    7070int8_t bmac_encryption_set_key(uint8_t *key, uint8_t len); 
    7171int8_t bmac_encryption_enable(); 
     72int8_t bmac_encryption_set_ctr_counter(uint8_t *counter, uint8_t len); 
    7273int8_t bmac_encryption_disable(); 
    7374int8_t bmac_rx_pkt_is_encrypted(); 

  • nano-RK/src/radio/cc2420/include/basic_rf.h

    r380 r389  
    7676uint8_t rf_security_last_pkt_status(); 
    7777void rf_security_set_key(uint8_t *key); 
     78void rf_security_set_ctr_counter(uint8_t *counter); 
    7879void rf_security_enable(); 
    7980void rf_security_disable(); 

  • nano-RK/src/radio/cc2420/source/basic_rf.c

    r383 r389  
    4444uint8_t last_pkt_encrypted; 
    4545uint16_t mdmctrl0; 
     46uint8_t tx_ctr[4]; 
     47uint8_t rx_ctr[4]; 
    4648 
    4749// Returns 1 if the last packet was encrypted, 0 otherwise 
    …… 
    5052return last_pkt_encrypted; 
    5153} 
     54 
     55 
     56void rf_security_set_ctr_counter(uint8_t *counter) 
     57{ 
     58uint8_t n; 
     59// CTR counter value 
     60FASTSPI_WRITE_RAM(&counter[0],(CC2420RAM_TXNONCE+9),2,n);  
     61FASTSPI_WRITE_RAM(&counter[2],(CC2420RAM_TXNONCE+11),2,n);  
     62tx_ctr[0]=counter[0]; 
     63tx_ctr[1]=counter[1]; 
     64tx_ctr[2]=counter[2]; 
     65tx_ctr[3]=counter[3]; 
     66} 
     67 
    5268 
    5369void rf_security_set_key(uint8_t *key) 
    …… 
    6581        } 
    6682 
    67 // Set AES nonce 
     83// Set AES nonce to all zeros 
    6884nrk_spin_wait_us(100);  
    69 for(i=0; i<8; i++ ) 
     85for(i=0; i<7; i++ ) 
    7086        { 
    7187        key_buf=0;  
    72         nrk_spin_wait_us(100);  
    7388        FASTSPI_WRITE_RAM_LE(&key_buf,(CC2420RAM_TXNONCE+(i*2)),2,n);  
    74         nrk_spin_wait_us(100);  
    7589        FASTSPI_WRITE_RAM_LE(&key_buf,(CC2420RAM_RXNONCE+(i*2)),2,n);  
    7690        } 
     91        // block counter set 1 
     92        key_buf=1;  
     93        FASTSPI_WRITE_RAM_LE(&key_buf,(CC2420RAM_TXNONCE+14),2,n);  
     94        FASTSPI_WRITE_RAM_LE(&key_buf,(CC2420RAM_RXNONCE+14),2,n);  
    7795} 
    7896 
    …… 
    8098{ 
    8199    FASTSPI_SETREG(CC2420_SECCTRL0, 0x0306); // Enable CTR encryption with key 0 
    82     FASTSPI_SETREG(CC2420_SECCTRL1, 0x0a0a); // Encrypt / Decrypt 6 bytes into header 
     100    FASTSPI_SETREG(CC2420_SECCTRL1, 0x0e0e); // Encrypt / Decrypt 18 bytes into header 
    83101 
    84102security_enable=1; 
    …… 
    606624    // Slots for example are at a slighly higher later since they assume TDMA 
    607625    packetLength = pRTI->length + RF_PACKET_OVERHEAD_SIZE + CHECKSUM_OVERHEAD; 
     626    if(security_enable) packetLength+=4;  // for CTR counter 
    608627 
    609628 
    …… 
    647666    FASTSPI_WRITE_FIFO((uint8_t*) &pRTI->destAddr, 2);            // Dest. address 
    648667    FASTSPI_WRITE_FIFO((uint8_t*) &rfSettings.myAddr, 2);         // Source address 
     668    if(security_enable) 
     669        FASTSPI_WRITE_FIFO((uint8_t*) &tx_ctr, 4);         // CTR counter  
     670    
    649671    FASTSPI_WRITE_FIFO((uint8_t*) pRTI->pPayload, pRTI->length);  // Payload 
    650672    FASTSPI_WRITE_FIFO((uint8_t*) &checksum, 1);         // Checksum 
    …… 
    763785return SFD_IS_1; 
    764786} 
     787uint16_t tmp_blah; 
    765788 
    766789int8_t rf_polling_rx_packet() 
    …… 
    850873*/ 
    851874                        // Skip the destination PAN and address (that's taken care of by harware address recognition!) 
    852                 if(frameControlField & RF_SEC_BM) 
     875                FASTSPI_READ_FIFO_GARBAGE(4); 
     876 
     877                        // Read the source address 
     878                        FASTSPI_READ_FIFO_NO_WAIT((uint8_t*) &rfSettings.pRxInfo->srcAddr, 2); 
     879 
     880                        if(frameControlField & RF_SEC_BM) 
    853881                        { 
     882                                uint8_t n; 
     883                                // READ rx_ctr and set it 
     884                                FASTSPI_READ_FIFO_NO_WAIT((uint8_t*) &rx_ctr, 4); 
     885                                FASTSPI_WRITE_RAM(&rx_ctr[0],(CC2420RAM_RXNONCE+9),2,n);  
     886                                FASTSPI_WRITE_RAM(&rx_ctr[2],(CC2420RAM_RXNONCE+11),2,n);  
    854887                                FASTSPI_STROBE(CC2420_SRXDEC);  // if packet is encrypted then decrypt  
    855888                                last_pkt_encrypted=1; 
     889                                rfSettings.pRxInfo->length -= 4; 
    856890                        } 
    857                         FASTSPI_READ_FIFO_GARBAGE(4); 
    858  
    859                         // Read the source address 
    860                         FASTSPI_READ_FIFO_NO_WAIT((uint8_t*) &rfSettings.pRxInfo->srcAddr, 2); 
    861  
     891         
    862892                        // Read the packet payload 
    863893                        FASTSPI_READ_FIFO_NO_WAIT(rfSettings.pRxInfo->pPayload, rfSettings.pRxInfo->length);