Changeset 95
- Timestamp:
- 06/12/2007 06:42:37 PM (5 years ago)
- Location:
- nano-RK
- Files:
-
- 7 added
- 12 edited
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include/common.mk (modified) (1 diff)
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projects/basic_bmac/makefile (modified) (1 diff)
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projects/basic_tasks/nrk_cfg.h (modified) (1 diff)
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src/drivers/include/nrk_driver_list.h (modified) (1 diff)
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src/drivers/platform/firefly2_2 (added)
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src/drivers/platform/firefly2_2/include (added)
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src/drivers/platform/firefly2_2/include/adc_driver.h (added)
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src/drivers/platform/firefly2_2/include/ff_basic_sensor.h (added)
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src/drivers/platform/firefly2_2/source (added)
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src/drivers/platform/firefly2_2/source/adc_driver.c (added)
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src/drivers/platform/firefly2_2/source/ff_basic_sensor.c (added)
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src/kernel/hal/atmega1281/nrk_timer.c (modified) (5 diffs)
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src/kernel/include/nrk_cpu.h (modified) (1 diff)
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src/kernel/include/nrk_driver.h (modified) (1 diff)
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src/kernel/source/nrk.c (modified) (1 diff)
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src/kernel/source/nrk_driver.c (modified) (1 diff)
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src/kernel/source/nrk_scheduler.c (modified) (4 diffs)
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src/platform/firefly2_2/include/hal.h (modified) (1 diff)
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src/platform/firefly2_2/include/hal_firefly2_2.h (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
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nano-RK/include/common.mk
r57 r95 151 151 # Set these parameters for the micaZ 152 152 UISP = uisp 153 UISP_FLAGS = -dprog=mib510 -dserial= /dev/ttyS0--wr_fuse_h=0xd8 -dpart=ATmega128 --wr_fuse_e=ff --erase --upload if=$(TARGET).srec153 UISP_FLAGS = -dprog=mib510 -dserial=$(PROGRAMMING_PORT) --wr_fuse_h=0xd8 -dpart=ATmega128 --wr_fuse_e=ff --erase --upload if=$(TARGET).srec 154 154 155 155 ################################# AVR DUDE SETTINGS ########################## -
nano-RK/projects/basic_bmac/makefile
r51 r95 1 1 # Platform name cc2420DK, firefly, micaZ 2 PLATFORM = firefly2 2 PLATFORM = firefly2_2 3 3 4 4 -
nano-RK/projects/basic_tasks/nrk_cfg.h
r94 r95 10 10 // NRK_HALT_ON_ERRORS will cause the kernel to freeze on errors so that 11 11 // it is easier to see debugging messages. 12 //#define NRK_HALT_AND_LOOP_ON_ERROR12 #define NRK_HALT_AND_LOOP_ON_ERROR 13 13 14 14 // If you want to disable the looping kernel error message when the system 15 15 // halts, then include the following define. This will automatically 16 16 // halt the error as well. 17 #define NRK_HALT_ON_ERROR17 //#define NRK_HALT_ON_ERROR 18 18 19 19 // NRK_STACK_CHECK adds a little check to see if the bottom of the stack -
nano-RK/src/drivers/include/nrk_driver_list.h
r15 r95 31 31 32 32 // DEVICE ID ASSIGNMENTS 33 #define FIREFLY_SENSORS 1 34 #define ADC_DEV_MANAGER 135 #define QLIGHT_DEV0 233 // These ids must be known by the implementation of the driver 34 #define ADC_DEV_MANAGER 0 35 #define FIREFLY_SENSOR_BASIC 1 36 36 37 37 38 // Typical Driver States39 #define INIT_STATE 040 #define OPEN_STATE 141 #define CLOSE_STATE 242 #define HIGH_FREQ 343 #define STDIO 344 #define STATUS 745 38 46 47 //First level of direction primitives48 #define READ_STATE STDIO + 149 #define READ READ_STATE50 #define WRITE_STATE STDIO + 251 #define WRITE WRITE_STATE52 #define RW_STATE STDIO + 353 #define READ_WRITE RW_STATE54 55 -
nano-RK/src/kernel/hal/atmega1281/nrk_timer.c
r15 r95 56 56 OCR2A = _nrk_prev_timer_val; 57 57 TIFR2 = BM(OCF2A) | BM(TOV2); // Clear interrupt flag 58 // TIMSK = BM(OCIE0) | BM(TOIE0) ;//| BM(TICIE1); // Enable interrupt59 //TCCR0 = BM(WGM01) | BM(CS02) | BM(CS00); //| // reset counter on interrupt, set divider to 12860 58 TCCR2A = BM(WGM21); 61 59 TCCR2B = BM(CS21) | BM(CS20); //| // reset counter on interrupt, set divider to 128 62 60 GTCCR |= BM(PSRASY); // reset prescaler 63 //GTCCR |= TSM; // reset prescaler64 #ifdef NRK_DRIVER_CNTs65 ETIFR = BM(OCF3A); // Clear interrupt flag66 TIMSK = BM(OCIE3A);//| BM(TICIE1); // Enable interrupt67 TCCR3A = BM(WGM32)|BM(CS32); //| // reset counter on interrupt, set divider to 12868 OCR3AH=0x00;69 OCR3AL=250;70 #endif71 61 // Clear interrupt flag 72 62 TIFR2 = BM(OCF2A) | BM(TOV2); … … 147 137 void _nrk_start_raw_timer() 148 138 { 149 //SFIOR |= BM(PSR2); // reset prescaler150 139 GTCCR |= BM(PSRASY); // reset prescaler 151 140 TCNT2 = 0; // reset counter 152 141 TIMSK2 |= BM(OCIE2A) | BM(TOIE2) ;//| BM(TICIE1); // Enable interrupt 153 /*154 printf( "starting timer\r\n" );155 do{156 printf( "timer = %d\r\n",(volatile)TCNT2);157 }while(1);*/158 142 } 159 143 … … 163 147 164 148 GTCCR |= BM(PSRASY); // reset prescaler 165 //SFIOR |= BM(PSR2); // reset prescaler166 149 TCNT2 = 0; // reset counter 167 150 _nrk_time_trigger=0; … … 192 175 SIGNAL(__vector_default) { 193 176 nrk_kernel_error_add(NRK_SEG_FAULT,0); 194 //printf("Seg Fault");195 177 while(1); 196 178 } 197 179 198 #ifdef NRK_MAX_DRIVER_CNT199 SIGNAL(SIG_OUTPUT_COMPARE3A)200 {201 nrk_high_freq_driver_scheduler();202 return;203 204 }205 #endif206 180 SIGNAL(TIMER2_OVF_vect) { 207 181 208 182 nrk_kernel_error_add(NRK_TIMER_OVERFLOW,0); 209 // nrk_kprintf( "\r\n*Timer overflow!!!\r\n" );210 // SET_LED_0();211 // SET_LED_1();212 // SET_LED_2();213 while(1);214 183 return; 215 184 } 216 185 217 186 SIGNAL(TIMER2_COMPA_vect) { 218 //static uint8_t i=0;219 //_nrk_time_trigger++;220 /* if(i==0 ) {221 SET_LED_2();222 i=1;223 }else224 {225 CLR_LED_2();226 i=0;227 }228 */229 // printf( "Timer 2 interrup fired!\r\n" );230 187 _nrk_timer_suspend_task(); 231 188 return; … … 237 194 //------------------------------------------------------------------------------------------------------- 238 195 SIGNAL(SIG_OUTPUT_COMPARE1A) { 239 static uint8_t i=0;240 196 241 CLR_LED_1();242 if(i==0 ) {243 244 SET_LED_0();245 i=1;246 }else247 {248 CLR_LED_0();249 i=0;250 251 }252 253 //SuspendTask2();254 197 return; 255 198 } -
nano-RK/src/kernel/include/nrk_cpu.h
r15 r95 42 42 43 43 // This is the deep sleep wakeup penalty... 44 #define _NRK_SLEEP_WAKEUP_TIME 1 044 #define _NRK_SLEEP_WAKEUP_TIME 15 45 45 46 46 -
nano-RK/src/kernel/include/nrk_driver.h
r15 r95 34 34 #define NRK_DRIVER_H 35 35 36 #define NRK_FREQ_DRIVER 0 37 #define NRK_GPIO_DRIVER 1 38 #define OPEN 0 39 #define CLOSE 1 36 #include <stdint.h> 37 38 // Driver Open/Close 39 #define WAS_OPEN 1 40 #define WAS_NOT_OPEN 0 41 42 43 // Driver Actions 44 #define INIT 0 45 #define OPEN 1 46 #define CLOSE 2 47 #define GET_STATUS 3 48 #define SET_STATUS 4 49 #define READ 5 50 #define WRITE 6 51 52 // Access Privileges Bits 53 #define READ_FLAG 1 54 #define WRITE_FLAG 2 55 #define APPEND_FLAG 4 56 40 57 41 58 typedef struct nrk_driver 42 59 { 43 uint8_t dev_id; /* for enabling and disabling device drivers */ 44 uint16_t type;/* type of driver GPIO or fast frequency drivers*/ 45 uint8_t (*devicemanager)(uint8_t state,uint8_t opt,uint8_t*buf,uint8_t size);/*function pointer to the driver call*/ 60 int8_t dev_id; 61 // for enabling and disabling device drivers 62 int8_t access_priv; 63 // Access privileges (read, write, append etc) 64 int8_t (*devicemanager)(uint8_t state,uint8_t opt,uint8_t*buf,uint8_t size); 65 // function pointer to the driver call 46 66 47 }NRKDriver; 67 } NRKDriver; 68 48 69 49 70 int8_t nrk_register_driver(void *devicemanager,uint8_t driver_name); 50 //int8_t nrk_register_driver(void(*devicemanager()),uitn8_t driver_name);51 //int8_t nrk_register_driver(uint8_t *devicemanager,uint8_t driver_name);52 71 int8_t nrk_open(uint8_t dev_id,uint8_t opt); // options provide the ablility to set_status 53 uint8_t nrk_read(uint8_t dev_fd,uint8_t *buffer,uint8_t size); 54 uint8_t nrk_write(uint8_t dev_fd,uint8_t opt); 55 uint8_t nrk_close(uint8_t dev_fd); // options provide the ablility to set_status 56 uint8_t nrk_check_high_freq(); 57 uint8_t nrk_high_freq_driver_scheduler(); 58 uint8_t nrk_driver_set_high_freq(uint8_t dev_id,uint16_t freq); 59 uint8_t nrk_driver_stop_high_freq(uint8_t dev_id); 60 uint8_t nrk_set_status(uint8_t dev_fd,uint8_t key,uint8_t value); 61 uint8_t nrk_get_status(uint8_t dev_fd,uint8_t key); 72 int8_t nrk_read(uint8_t dev_fd,uint8_t *buffer,uint8_t size); 73 int8_t nrk_write(uint8_t dev_fd,uint8_t *buffer, uint8_t size); 74 int8_t nrk_close(uint8_t dev_fd); // options provide the ablility to set_status 75 int8_t nrk_set_status(uint8_t dev_fd,uint8_t key,uint8_t value); 76 int8_t nrk_get_status(uint8_t dev_fd,uint8_t key); 62 77 63 78 #endif -
nano-RK/src/kernel/source/nrk.c
r89 r95 77 77 #endif 78 78 79 nrk_led_clr(ORANGE_LED); 80 nrk_led_clr(BLUE_LED); 81 nrk_led_set(GREEN_LED); 82 nrk_led_clr(RED_LED); 83 84 79 85 #ifdef KERNEL_STK_ARRAY 80 86 stkc = (uint16_t*)&nrk_kernel_stk[NRK_KERNEL_STACKSIZE-1]; -
nano-RK/src/kernel/source/nrk_driver.c
r15 r95 50 50 51 51 NRKDriver nrk_drivers[NRK_MAX_DRIVER_CNT]; 52 uint8_t driver_record_init[NRK_MAX_DRIVER_CNT]; /*keep track of the the driver state post initialization;*/ 53 uint8_t _nrk_driver_count; 54 uint8_t NRKHighFreqDriverSchedule; 55 uint8_t NRKHighFreqDriverCurrSchedule; 52 uint8_t nrk_driver_init[NRK_MAX_DRIVER_CNT]; 56 53 57 int8_t nrk_register_driver(void *devicemanager,uint8_t driver_name) 54 int8_t _nrk_driver_count; 55 56 /* 57 * nrk_register_driver() 58 * 59 * This function takes a pointer to the entrance of a driver function 60 * and returns a device handler for the driver. 61 * 62 * 63 */ 64 65 int8_t nrk_register_driver(void *devicemanager,uint8_t dev_index) 58 66 { 59 67 if(_nrk_driver_count<NRK_MAX_DRIVER_CNT) 60 68 { 61 nrk_drivers[_nrk_driver_count].dev_id=d river_name;69 nrk_drivers[_nrk_driver_count].dev_id=dev_index; 62 70 nrk_drivers[_nrk_driver_count].devicemanager=(void*)devicemanager; 63 71 _nrk_driver_count++; 64 return 1;72 return NRK_OK; 65 73 } 66 74 else 67 return -1;75 return NRK_ERROR; 68 76 } 69 // create READ_STATE WRITE_STATE READ_WRITE_STATE CLOSE_STATE 70 /*limit only 127 open devices at once.*/ // returns file descriptor 71 int8_t nrk_open(uint8_t dev_i d,uint8_t opt) // options provide the ablility to set_status77 78 79 int8_t nrk_open(uint8_t dev_index,uint8_t opt) 72 80 { 73 uint8_t cnt; 81 uint8_t cnt; 82 83 74 84 for(cnt=0;cnt<_nrk_driver_count;cnt++) 75 85 { 76 if(nrk_drivers[cnt].dev_id==dev_i d)86 if(nrk_drivers[cnt].dev_id==dev_index) 77 87 { 78 if(!driver_record_init[cnt])88 if(nrk_driver_init[cnt]==WAS_NOT_OPEN) 79 89 { 80 driver_record_init[cnt]=1; 81 nrk_drivers[cnt].devicemanager(INIT_STATE,opt,NULL,0); 90 // Only call init the first time driver is opened 91 nrk_driver_init[cnt]=WAS_OPEN; 92 nrk_drivers[cnt].devicemanager(INIT,opt,NULL,0); 82 93 } 83 nrk_drivers[cnt].devicemanager(OPEN _STATE,opt,NULL,0);94 nrk_drivers[cnt].devicemanager(OPEN,opt,NULL,0); 84 95 return cnt; 85 96 } 86 97 } 87 return -1; 98 99 return NRK_ERROR; 88 100 } 89 101 90 uint8_t nrk_close(uint8_t dev_fd)102 int8_t nrk_close(uint8_t dev_fd) 91 103 { 92 /*causes the device to be reinitialized once its been closed*/ 93 uint8_t error=nrk_drivers[dev_fd].devicemanager(CLOSE_STATE,0,NULL,0); 94 if(!error) 95 driver_record_init[dev_fd]=0; 96 97 return error; 104 uint8_t error; 105 106 if(dev_fd<0 || dev_fd>_nrk_driver_count) 107 { 108 _nrk_errno_set(1); // invalid device 109 return NRK_ERROR; 110 } 111 112 error=nrk_drivers[dev_fd].devicemanager(CLOSE,0,NULL,0); 113 114 // Do we need to do init on a second reopen? 115 //if(!error) 116 // driver_record_init[dev_fd]=0; 117 118 return error; 98 119 } 99 120 100 121 101 uint8_t nrk_read(uint8_t dev_fd,uint8_t *buffer,uint8_t size)122 int8_t nrk_write(uint8_t dev_fd,uint8_t *buffer, uint8_t size) 102 123 { 124 if(dev_fd<0 || dev_fd>_nrk_driver_count) 125 { 126 _nrk_errno_set(1); // invalid device 127 return NRK_ERROR; 128 } 103 129 130 return nrk_drivers[dev_fd].devicemanager(WRITE,0,buffer,size); 104 131 105 return nrk_drivers[dev_fd].devicemanager(READ_STATE,0,buffer,size); 132 } 133 134 int8_t nrk_read(uint8_t dev_fd,uint8_t *buffer,uint8_t size) 135 { 136 if(dev_fd<0 || dev_fd>_nrk_driver_count) 137 { 138 _nrk_errno_set(1); // invalid device 139 return NRK_ERROR; 140 } 141 142 return nrk_drivers[dev_fd].devicemanager(READ,0,buffer,size); 106 143 107 144 } 108 145 /*if key is 0 then assumed to create a frequency setting*/ 109 uint8_t nrk_set_status(uint8_t dev_fd,uint8_t key,uint8_t value)146 int8_t nrk_set_status(uint8_t dev_fd,uint8_t key,uint8_t value) 110 147 { 111 return nrk_drivers[dev_fd].devicemanager(key,value,NULL,0); 148 if(dev_fd<0 || dev_fd>_nrk_driver_count) 149 { 150 _nrk_errno_set(1); // invalid device 151 return NRK_ERROR; 152 } 153 return nrk_drivers[dev_fd].devicemanager(SET_STATUS,key,NULL,value); 112 154 } 113 155 114 uint8_t nrk_get_status(uint8_t dev_fd,uint8_t key)156 int8_t nrk_get_status(uint8_t dev_fd,uint8_t key) 115 157 { 116 return nrk_drivers[dev_fd].devicemanager(key,0,NULL,0); 158 if(dev_fd<0 || dev_fd>_nrk_driver_count) 159 { 160 _nrk_errno_set(1); // invalid device 161 return NRK_ERROR; 162 } 163 164 return nrk_drivers[dev_fd].devicemanager(GET_STATUS,key,NULL,0); 117 165 } 118 uint8_t nrk_driver_set_high_freq(uint8_t dev_id,uint16_t freq)119 {120 uint8_t i;121 /*timer 2 setup*/122 #ifdef NRK_DRIVER_FREQ123 /* if(!nrk_check_high_freq())124 {125 * TIMSK=BM(OCIE1A)|BM(OCIE0);126 TCCR0=BM(WGM01) | BM(CS01);127 TCNT0=0x00;128 OCR0=(uint16_t)(NRK_DRIVER_FREQ*100)/32;129 } i*/130 for(i=0;i<NRK_MAX_DRIVER_CNT;i++)131 if(nrk_drivers[i].dev_id==dev_id)132 nrk_drivers[i].type=freq/NRK_DRIVER_FREQ;133 134 if(NRKHighFreqDriverSchedule > nrk_drivers[i].type)135 NRKHighFreqDriverSchedule=nrk_drivers[i].type;136 return nrk_drivers[i].type;137 #else138 return 0;139 #endif140 }141 uint8_t nrk_driver_stop_high_freq(uint8_t dev_id)142 {143 uint8_t i;144 for(i=0;i<NRK_MAX_DRIVER_CNT;i++)145 if(nrk_drivers[i].dev_id==dev_id)146 {147 nrk_drivers[i].type=0;148 if(!nrk_check_high_freq())149 TIMSK=BM(OCIE1A);150 return 0;151 }152 return 1;153 }154 uint8_t nrk_check_high_freq()155 {156 166 157 uint8_t i=0;158 for(i=0;i<_nrk_driver_count;i++)159 if(nrk_drivers[i].type > 0)160 return 1;161 162 return 0;163 164 }165 uint8_t nrk_high_freq_driver_scheduler()166 {167 uint8_t i=0;168 169 for(i=0;i<_nrk_driver_count;i++)170 {171 if(nrk_drivers[i].type)172 {173 if(!(NRKHighFreqDriverCurrSchedule%nrk_drivers[i].type)) nrk_drivers[i].devicemanager(HIGH_FREQ,0,NULL,0);174 }175 }176 if(NRKHighFreqDriverSchedule==NRKHighFreqDriverCurrSchedule)177 NRKHighFreqDriverCurrSchedule=1;178 else179 NRKHighFreqDriverCurrSchedule++;180 return 0;181 }182 167 #endif -
nano-RK/src/kernel/source/nrk_scheduler.c
r87 r95 47 47 // 800 * .125 = 100us 48 48 #define CONTEXT_SWAP_TIME_BOUND 750 49 49 #define MAX_WAKEUP_TIME 254 50 50 51 51 void inline _nrk_scheduler() … … 65 65 // Lets handle the timing stuff here. Make sure your clock is good to go... 66 66 //TIMSK = BM (OCIE1A) | BM(OCIE0); 67 next_wake= 254;67 next_wake=MAX_WAKEUP_TIME; 68 68 _nrk_set_next_wakeup(next_wake); 69 69 start_time_stamp=_nrk_get_high_speed_timer(); … … 191 191 { 192 192 // You are a non-Idle Task 193 if(nrk_task_TCB[task_ID].cpu_reserve!=0 && nrk_task_TCB[task_ID].cpu_remaining< 254)193 if(nrk_task_TCB[task_ID].cpu_reserve!=0 && nrk_task_TCB[task_ID].cpu_remaining<MAX_WAKEUP_TIME) 194 194 { 195 195 if(next_wake>nrk_task_TCB[task_ID].cpu_remaining) … … 198 198 else 199 199 { 200 if(next_wake> 254) next_wake=254;200 if(next_wake>MAX_WAKEUP_TIME) next_wake=MAX_WAKEUP_TIME; 201 201 } 202 202 } -
nano-RK/src/platform/firefly2_2/include/hal.h
r94 r95 402 402 403 403 404 405 406 /*******************************************************************************************************407 *******************************************************************************************************408 ************************** ADC **************************409 *******************************************************************************************************410 *******************************************************************************************************/411 412 413 //-------------------------------------------------------------------------------------------------------414 // ADC initialization415 #define ADC_INIT() \416 do { \417 ADCSRA = BM(ADPS0) | BM(ADPS1) | BM(ADFR); \418 ADMUX = BM(REFS0); \419 } while (0)420 421 /*422 #define ADC_INIT() \423 do { \424 ADCSRA = BM(ADPS0) | BM(ADPS1) | BM(ADIF); \425 ADMUX = BM(REFS0); \426 } while (0)427 */428 429 // Selects which ADC channel to use. The channels (0-3) are defined in the development board definition430 // files, e.g. hal_cc2420db.h, as ADC_INPUT_...431 #define ADC_SET_CHANNEL(channel) do { ADMUX = (ADMUX & ~0x1F) | (channel); } while (0)432 433 // Enables/disables the ADC434 #define ADC_ENABLE() do { ADCSRA |= BM(ADEN); } while (0)435 #define ADC_DISABLE() do { ADCSRA &= ~BM(ADEN); } while (0)436 //-------------------------------------------------------------------------------------------------------437 438 439 //-------------------------------------------------------------------------------------------------------440 // ADC sampling441 442 // Macro for taking a single sample in single-conversion mode (not required in continuous mode)443 #define ADC_SAMPLE_SINGLE() \444 do { \445 ADCSRA |= BM(ADSC); \446 while (!(ADCSRA & 0x10)); \447 } while(0)448 449 // Macros for obtaining the latest sample value450 #define ADC_GET_SAMPLE_10(x) \451 do { \452 x = ADCL; \453 x |= ADCH << 8; \454 } while (0)455 456 #define ADC_GET_SAMPLE_8(x) \457 do { \458 x = ((uint8_t) ADCL) >> 2; \459 x |= ((int8_t) ADCH) << 6; \460 } while (0)461 //-------------------------------------------------------------------------------------------------------462 404 463 405 -
nano-RK/src/platform/firefly2_2/include/hal_firefly2_2.h
r38 r95 52 52 #define FIREFLY2_2_PLATFORM 53 53 54 #define NRK_DEFAULT_UART 1 55 54 56 #define RED_LED 3 55 57 #define GREEN_LED 2 56 58 #define BLUE_LED 1 57 59 #define ORANGE_LED 0 58 59 60 #define NRK_DEFAULT_UART 161 /*******************************************************************************************************62 *******************************************************************************************************63 ************************** AVR I/O PORTS **************************64 *******************************************************************************************************65 *******************************************************************************************************/66 67 //---------------------------------------------------------------------------------------------68 // Port A69 #define VREG_EN 5 // PA.5 - Output: VREG_EN to CC242070 #define RESET_N 6 // PA.6 - Output: RESET_N to CC242071 #define DEBUG_0 372 #define DEBUG_1 473 74 //---------------------------------------------------------------------------------------------75 // Port B76 #define SPI_SS 0 // PB.0 - Output: SPI Slave Select77 #define SCK 1 // PB.1 - Output: SPI Serial Clock (SCLK)78 #define MOSI 2 // PB.2 - Output: SPI Master out - slave in (MOSI)79 #define MISO 3 // PB.3 - Input: SPI Master in - slave out (MISO)80 //---------------------------------------------------------------------------------------------81 //PORT C82 #define CSN 0 // PB.0 - Output: SPI Chip Select (CS_N)83 #define FIFO 1 // PB.7 - Input: FIFO from CC242084 85 86 //---------------------------------------------------------------------------------------------87 // Clears LED88 #define CLR_LED_0() (PORTE |= BM(YLED))89 #define CLR_LED_1() (PORTE |= BM(GLED))90 #define CLR_LED_2() (PORTE |= BM(RLED))91 #define CLR_LED_3() (PORTE |= BM(BLED))92 93 // Set LED94 #define SET_LED_0() (PORTE &= ~BM(YLED))95 #define SET_LED_1() (PORTE &= ~BM(GLED))96 #define SET_LED_2() (PORTE &= ~BM(RLED))97 #define SET_LED_3() (PORTE &= ~BM(BLED))98 //---------------------------------------------------------------------------------------------99 // Port D100 #define UART1_RXD 2 // PD.2 - Input: UART1 RXD101 #define UART1_TXD 3 // PD.3 - Output: UART1 TXD102 #define SFD 6 // PD.4 - Input: SFD from CC2420103 #define UART1_RTS 5 // PD.5 - Output: UART HW handshaking: RTS104 #define CCA 4 // PD.6 - Input: CCA from CC2420105 #define UART1_CTS 7 // PD.7 - Input: UART HW handshaking: CTS106 107 //----------------------------------------------------------------------------------------------108 109 110 //----------------------------------------------------------------------------------------------111 // Port E112 #define UART0_RXD 0 // PE.0 - Input: UART0 RXD113 #define UART0_TXD 1 // PE.1 - Output: UART0 TXD114 #define BUTTON 5 // PE.5 - Input : Push button S2115 #define FIFOP 7 // PE.7 - Input: FIFOP from CC2420116 #define YLED 2 // PA.0 - Output: Yellow LED117 #define GLED 3 // PA.1 - Output: Green LED118 #define RLED 4 // PA.2 - Output: Red LED119 #define BLED 5 // PA.2 - Output: Red LED120 //-------------------------------------------------------------------------------------------------------121 122 123 //-------------------------------------------------------------------------------------------------------124 // Port F125 #define JOYSTICK_LEFT 1 // PF.1 - Input: Joystick left126 #define JOYSTICK_DOWN 2 // PF.2 - Input: Joystick down127 128 // ADC inputs129 #define ADC_INPUT_0_POT_METER 0 // PF.0 - ADC0 with potentiometer130 #define ADC_INPUT_1 1 // PF.1 - ADC1131 #define ADC_INPUT_2 2 // PF.2 - ADC2132 #define ADC_INPUT_3_TEMP_SENSOR 3 // PF.3 - ADC3 with temp sensor133 134 // JTAG interface:135 // PF.4 - Input : JTAG TCK serial clock136 // PF.5 - Input : JTAG TMS strobe enable137 // PF.6 - Output: JTAG TDO serial data output138 // PF.7 - Input : JTAG TDI serial data input139 //-------------------------------------------------------------------------------------------------------140 141 142 //-------------------------------------------------------------------------------------------------------143 // Port G144 //-------------------------------------------------------------------------------------------------------145 146 147 //-------------------------------------------------------------------------------------------------------148 // External RAM interface:149 // PA and PC - Multiplexed address/data150 // PG.0 - Output: Write enable: WR_N151 // PG.1 - Output: Read enable: RD_N152 // PG.2 - Output: Address Latch Enable: ALE153 //-------------------------------------------------------------------------------------------------------154 155 156 //----------------------------------------------------------------------------------------------157 // Port setup macros158 60 159 61 // Port initialization … … 166 68 DDRC = BM(CSN); \ 167 69 PORTC = BM(CSN); \ 168 DDRE = BM(RLED) | BM(YLED) | BM(GLED) | BM(BLED) | BM(UART0_TXD); \ 70 DDRE = BM(RED_LED) | BM(ORANGE_LED) | BM(GREEN_LED) | BM(BLUE_LED) | BM(UART0_TXD); \ 71 DDRD = BM(UART1_TXD); \ 169 72 PORTE = BM(UART0_TXD); \ 170 73 DDRA = BM(VREG_EN) | BM(RESET_N) | BM(DEBUG_0) | BM(DEBUG_1); \ 171 74 PORTA = BM(RESET_N); \ 172 75 } while (0) 173 /*174 #define PORT_INIT() \175 do { \176 SFIOR |= BM(PUD); \177 DDRB = BM(RESET_N) | BM(VREG_EN) | BM(SCK) | BM(CSN) | BM(OLED) | BM(GLED); \178 PORTB = BM(RESET_N) | BM(SCK) | BM(CSN); \179 DDRD = BM(UART1_TXD) | BM(UART1_RTS); \180 PORTD = BM(UART1_RTS) | BM(UART1_CTS);\181 DDRE = BM(UART0_TXD) | BM(RLED) | BM(YLED); \182 PORTE = 0x00; \183 } while (0)184 */185 76 186 77 // Enables the external SRAM … … 195 86 196 87 197 /******************************************************************************************************* 198 ******************************************************************************************************* 199 ************************** CC2420 PIN ACCESS ************************** 200 ******************************************************************************************************* 201 *******************************************************************************************************/ 202 203 204 //------------------------------------------------------------------------------------------------------- 88 /****************************************************************************** 89 ****************************************************************************** 90 ************************** CC2420 PIN ACCESS 91 ****************************************************************************** 92 ******************************************************************************/ 205 93 // CC2420 pin access 206 94 … … 220 108 #define SET_VREG_ACTIVE() PORTA |= BM(VREG_EN) 221 109 #define SET_VREG_INACTIVE() PORTA &= ~BM(VREG_EN) 222 //--------------------------------------------------------------------------- ----------------------------110 //--------------------------------------------------------------------------- 223 111 224 112 225 113 226 114 227 /*******************************************************************************************************228 *******************************************************************************************************229 ************************** SERIAL PORTS **************************230 *******************************************************************************************************231 *******************************************************************************************************/232 115 233 234 //------------------------------------------------------------------------------------------------------- 235 // UART hardware flow control 236 #define CLR_RTS() (PORTD &= ~BM(UART1_RTS)) 237 #define SET_RTS() (PORTD |= BM(UART1_RTS)) 238 239 #define SET_CTS() (PORTD |= BM(UART1_CTS)) 240 #define CLR_CTS() (PORTD &= ~BM(UART1_CTS)) 241 //------------------------------------------------------------------------------------------------------- 242 243 244 245 246 /******************************************************************************************************* 247 ******************************************************************************************************* 248 ************************** EXTERNAL INTERRUPTS ************************** 249 ******************************************************************************************************* 250 *******************************************************************************************************/ 251 252 253 //------------------------------------------------------------------------------------------------------- 116 /***************************************************************************** 117 ***************************************************************************** 118 ************************** EXTERNAL INTERRUPTS 119 ****************************************************************************** 120 ******************************************************************************/ 254 121 // Rising edge trigger for external interrupt 0 (FIFOP) 255 122 #define FIFOP_INT_INIT() do { EICRA |= 0x03; CLEAR_FIFOP_INT(); } while (0) … … 270 137 271 138 272 //-------------------------------------------------------------------------------------------------------273 // Falling edge trigger for external interrupt 6 (joystick)274 #define JOYSTICK_INT_INIT() do { EICRB |= 0x20; } while (0)275 276 // Joystick on external interrupt 6277 #define ENABLE_JOYSTICK_INT() do { EIMSK |= 0x40; } while (0)278 #define DISABLE_JOYSTICK_INT() do { EIMSK &= ~0x40; } while (0)279 #define CLEAR_JOYSTICK_INT() do { EIFR = 0x40; } while (0)280 //-------------------------------------------------------------------------------------------------------281 282 283 284 285 /*******************************************************************************************************286 *******************************************************************************************************287 ************************** BUTTONS **************************288 *******************************************************************************************************289 *******************************************************************************************************/290 291 //-------------------------------------------------------------------------------------------------------292 // S2 button293 #define BUTTON_PRESSED() !(PINE & BM(BUTTON))294 295 // Joystick296 #define JOYSTICK_UP_PRESSED() (PINE & BM(JOYSTICK_UP))297 #define JOYSTICK_DOWN_PRESSED() (PINF & BM(JOYSTICK_DOWN))298 #define JOYSTICK_LEFT_PRESSED() (PINF & BM(JOYSTICK_LEFT))299 #define JOYSTICK_RIGHT_PRESSED() (PINE & BM(JOYSTICK_RIGHT))300 #define JOYSTICK_CENTER_PRESSED() (PINE & BM(JOYSTICK_CENTER))301 //-------------------------------------------------------------------------------------------------------302 303 304 305 306 /*******************************************************************************************************307 *******************************************************************************************************308 ************************** LEDS **************************309 *******************************************************************************************************310 *******************************************************************************************************/311 312 313 //-------------------------------------------------------------------------------------------------------314 // Clears LED315 #define CLR_GLED() (PORTB &= ~BM(GLED))316 #define CLR_OLED() (PORTB &= ~BM(OLED))317 #define CLR_YLED() (PORTE &= ~BM(YLED))318 #define CLR_RLED() (PORTE &= ~BM(RLED))319 320 // Set LED321 #define SET_GLED() (PORTB |= BM(GLED))322 #define SET_OLED() (PORTB |= BM(OLED))323 #define SET_YLED() (PORTE |= BM(YLED))324 #define SET_RLED() (PORTE |= BM(RLED))325 326 // Sets all leds simultaneously to display a 4-bit binary code327 #define SET_LED_MASK(n) \328 do { \329 if (n & 0x01) SET_GLED(); else CLR_GLED(); \330 if (n & 0x02) SET_OLED(); else CLR_OLED(); \331 if (n & 0x04) SET_RLED(); else CLR_RLED(); \332 if (n & 0x08) SET_YLED(); else CLR_YLED(); \333 } while (0)334 //-------------------------------------------------------------------------------------------------------335 336 337 338 339 /*******************************************************************************************************340 *******************************************************************************************************341 ************************** APPLICATION DEBUGGING **************************342 *******************************************************************************************************343 *******************************************************************************************************/344 345 346 //-------------------------------------------------------------------------------------------------------347 // Controlled application crash (flashes the LEDs forever to indicate an error code)348 #define EXCEPTION(n) \349 do { \350 DISABLE_GLOBAL_INT(); \351 SET_LED_MASK(n); \352 halWait(50000); \353 SET_LED_MASK(0); \354 halWait(50000); \355 } while (TRUE)356 //-------------------------------------------------------------------------------------------------------357 358 139 359 140 #endif
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